Assembly Code Cheat Sheet

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Assembly Cheatsheet. It's a great cheat sheet to helps you remember stuff in 8086 assembly programming. I used it to pass my assembly exam:) Content list. Code Structure; Intrupts. Working with strings; Working with files; Procedures; Time; Basic Structure. Each assembly program should start with this style below. Done:;- Assembly Label: address of next code or data line. AndDone;- Assembly Label: address of next code or data line. Halt;-x0207 = trap x25 data:.fill x00ff;-x0208 Asm directive: insert x00ff into this word. Buff:.blkw #4;-x0209 Asm directive: insert x0000 into 4 words. Msg:.stringz '12';-x020C =.fill x0031.fill x0032.fill x0000;- which is ascii '1' '2' NUL, left zero-extended. The conversion process is referred to as assembly, as in assembling the source code. Assembly language usually has one statement per machine instruction (1:1), but comments and statements that are assembler directives,macros, and symbolic labels of program and memory locations are often also supported. Assembly Language Cheat Sheet List.

  1. Assembly Code Cheat Sheet
  2. Assembly Code Cheat Sheet At&t X86 64

IA32 gnu Cheat Sheet Integer Registers (4 byte)%eip instruction pointer%esp stack pointer%ebp base pointer for stack frame%eax return values; low of pair for mul/div with%edx; intermediate%edx Signed Comparisons:high of pair for mul/div pair with%eax; intermediate%ecx intermediate%ebx base address for arrays; callee save.

All RISC-V processors must implement the base integer instruction set known under the acronym RV32I. The encoding of RISC-V base integer instructions is 32 bits wide. A RISC-V processor has 32 general purpose x-registers and a program counter register. This cheatsheet shows an overview of the assembly instructions.

registerABIdescription
pcpcprogram counter
registerABIdescriptionregisterABIdescription
x0zeroalways zerox16a6function argument 6
x1racall return addressx17a7function argument 7
x2spstack pointerx18s2saved register 2
x3gpglobal pointerx19s3saved register 3
x4tpthread pointerx20s4saved register 4
x5t0temporary register 0x21s5saved register 5
x6t1temporary register 1x22s6saved register 6
x7t2temporary register 2x23s7saved register 7
x8s0saved register 0x24s8saved register 8
x9s1saved register 1x25s9saved register 9
x10a0function argument 0x26s10saved register 10
x11a1function argument 1x27s11saved register 11
x12a2function argument 2x28t3temporary register 3
x13a3function argument 3x29t4temporary register 4
x14a4function argument 4x30t5temporary register 5
x15a5function argument 5x31t6temporary register 6

Acronyms

  • xD : Destination register x0…x31
  • xS : Source register x0…x31
  • xL : Left register x0…x31
  • xR : Right register x0…x31
  • xB : Base register x0…x31

Register-register instructions

mnemonicdestinationsource 1source 2description
registerregisterregister
ADDxD,xL,xRAdd
SUBxD,xL,xRSubtract
ANDxD,xL,xRAND
ORxD,xL,xROR
XORxD,xL,xRXOR
SLTxD,xL,xRSet Less Than
SLTUxD,xL,xRSet Less Than Unsigned
SLLxD,xL,xRShift Left Logical
SRLxD,xL,xRShift Right Logical
SRAxD,xL,xRShift Right Arithmetic

Immediate instructions

mnemonicdestinationsource 1immediatedescription
registerregister
ADDIxD,xL,CONSTANTAdd Immediate
ANDIxD,xL,CONSTANTAND Immediate
ORIxD,xL,CONSTANTOR Immediate
XORIxD,xL,CONSTANTXOR Immediate
SLTIxD,xL,CONSTANTSet Less Than Immediate
SLLIxD,xL,SHIFTShift Left Logical Immediate
SRLIxD,xL,SHIFTShift Right Logical Immediate
SRAIxD,xL,SHIFTShift Right Arithmetic Immediate

Conditional branches

Assembly Code Cheat Sheet
mnemonicsource 1source 2immediatedescription
registerregister
BEQxL,xR,OFFSETBranch Equal
BNExL,xR,OFFSETBranch Not Equal
BLTxL,xR,OFFSETBranch Less Than
BGExL,xR,OFFSETBranch Greater Equal
BLTUxL,xR,OFFSETBranch Less Than Unsigned
BGEUxL,xR,OFFSETBranch Greater Equal Unsigned

Upper immediate instructions

mnemonicdestinationimmediatedescription
register
LUIxD,UPPERLoad Upper Immediate
AUIPCxD,UPPERAdd Upper Immediate to PC

Unconditional jumps

mnemonicdestinationimmediatedescription
register
JALxD,OFFSETJump AND Link

Indirect jump instruction

mnemonicdestinationsource 1immediatedescription
registerregister
JALRxD,xL,OFFSETJump and Link Register

Load and store instruction

mnemonicdestinationimmediatesource 1description
registerregister
LBxD,OFFSET(xB)Load Byte
LHxD,OFFSET(xB)Load Half
LWxD,OFFSET(xB)Load Word
LBUxD,OFFSET(xB)Load Byte Unsigned
LHUxD,OFFSET(xB)Load Half Unsigned
mnemonicsource 2immediatesource 1description
registerregister
SBxS,OFFSET(xB)Store Byte
SHxS,OFFSET(xB)Store Half
SWxS,OFFSET(xB)Store Word
SBUxS,OFFSET(xB)Store Byte Unsigned
SHUxS,OFFSET(xB)Store Half Unsigned
Code

Memory ordering instructions

mnemonicpredecessorsuccessordescription
FENCEIORW,IORWFence
FENCE.IFence instruction
[31:25][24:20][19:15][14:12][11:7][6:0]
755357
function 7source 2source 1function 3destinationopcode
0000000xRxL000 : ADDxD0110011 : OP
0100000xRxL000 : SUBxD0110011 : OP
0000000xRxL001 : SLLxD0110011 : OP
0000000xRxL010 : SLTxD0110011 : OP
0000000xRxL011 : SLTUxD0110011 : OP
0000000xRxL100 : XORxD0110011 : OP
0000000xRxL101 : SRLxD0110011 : OP
0100000xRxL101 : SRAxD0110011 : OP
0000000xRxL110 : ORxD0110011 : OP
0000000xRxL111 : ANDxD0110011 : OP
[31:20][19:15][14:12][11:7][6:0]
125357
IMMEDIATE[11:0]source 1function 3destinationopcode
CONSTANT[11:0]xL000 : ADDIxD0010011 : OP-IMM
CONSTANT[11:0]xL010 : SLTIxD0010011 : OP-IMM
CONSTANT[11:0]xL011 : SLTIUxD0010011 : OP-IMM
CONSTANT[11:0]xL100 : XORIxD0010011 : OP-IMM
CONSTANT[11:0]xL110 : ORIxD0010011 : OP-IMM
CONSTANT[11:0]xL111 : ANDIxD0010011 : OP-IMM
[31:25][24:20][19:15][14:12][11:7][6:0]
755357
IMMEDIATE[11:5]IMMEDIATE[4:0]source 1function 3destinationopcode
0000000SHIFTxL001 : SLLIxD0010011 : OP-IMM
0000000SHIFTxL101 : SRLIxD0010011 : OP-IMM
0100000SHIFTxL101 : SRAIxD0010011 : OP-IMM
[31][30:25][24:20][19:15][14:12][11:8][7][6:0]
16553417
I[12]I[10:5]source 2source 1function 3I[4:1]I[11]opcode
O[12]O[10:5]xRxL000 : BEQO[4:1]O[11]1100011 : BRANCH
O[12]O[10:5]xRxL001 : BNEO[4:1]O[11]1100011 : BRANCH
O[12]O[10:5]xRxL100 : BLTO[4:1]O[11]1100011 : BRANCH
O[12]O[10:5]xRxL101 : BGEO[4:1]O[11]1100011 : BRANCH
O[12]O[10:5]xRxL110 : BLTUO[4:1]O[11]1100011 : BRANCH
O[12]O[10:5]xRxL111 : BGEUO[4:1]O[11]1100011 : BRANCH
[31:12][11:7][6:0]
2057
IMMEDIATE[31:12]destinationopcode
UPPER[31:12]xD0110111 : LUI
UPPER[31:12]xD0010111 : AUIPC

Assembly Code Cheat Sheet

[31][30:21][20][19:12][11:7][6:0]
1101857
I[20]I[10:1]I[11]IMMEDIATE[19:12]destinationopcode
O[20]O[10:1]O[11]O[19:12]xD1101111 : JAL
[31:20][19:15][14:12][11:7][6:0]
125357
IMMEDIATE[11:0]source 1function 3destinationopcode
OFFSET[11:0]xL0xD1100111 : JALR
[31:20][19:15][14:12][11:7][6:0]
125357
IMMEDIATE[11:0]source 1function 3destinationopcode
OFFSET[11:0]xB000 : LBxD0000011 : LOAD
OFFSET[11:0]xB001 : LHxD0000011 : LOAD
OFFSET[11:0]xB010 : LWxD0000011 : LOAD
OFFSET[11:0]xB100 : LBUxD0000011 : LOAD
OFFSET[11:0]xB101 : LHUxD0000011 : LOAD
[31:25][24:20][19:15][14:12][11:7][6:0]
755357
IMMEDIATE[11:5]source 2source 1function 3IMMEDIATE[4:0]opcode
OFFSET[11:5]xSxB000 : SBOFFSET0100011 : STORE
OFFSET[11:5]xSxB001 : SHOFFSET0100011 : STORE
OFFSET[11:5]xSxB010 : SWOFFSET0100011 : STORE
OFFSET[11:5]xSxB100 : SBUOFFSET0100011 : STORE
OFFSET[11:5]xSxB101 : SHUOFFSET0100011 : STORE

Assembly Code Cheat Sheet At&t X86 64

[31:28][27][26][25][24][23][22][21][20][19:15][14:12][11:7][6:0]
4111111115357
FMPIPOPRPWSISOSRSWsource 1function 3destinationopcode
0000PIPOPRPWSISOSRSW00000000: FENCE000000001111 : MISC-MEM
00000000000000000001: FENCE.I000000001111 : MISC-MEM